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8
7
6
5
4
3
2
1
{4} EBI1_FLASH_D[0..15]
{4} EBI1_FLASH_A[1..21]
{4} EBI1_DDR_D[0..15]
{4} EBI1_DDR_A[2..15]
DQ0
DQ1
DQ0
DQ1
D
C
{4} BA0_EBI1
{4} BA1_EBI1
{4} CKE_EBI1
{4} CLK_EBI1
{4} NCLK_EBI1
{4} CS_EBI1
{4} CAS_EBI1
{4} RAS_EBI1
{4} W E_EBI1
EBI1_DDR_A2 H8
EBI1_DDR_A3 H3
EBI1_DDR_A4 H7
EBI1_DDR_A5 J2
EBI1_DDR_A6 J8
EBI1_DDR_A7 J3
EBI1_DDR_A8 J7
EBI1_DDR_A9 K2
EBI1_DDR_A10 K8
EBI1_DDR_A11 K3
EBI1_DDR_A12 (SDA10) H2
EBI1_DDR_A13 K7
EBI1_DDR_A14 L2
EBI1_DDR_A15 L8
BA0_EBI1 G2
BA1_EBI1 G3
F9
CKE_EBI1 F2
CLK_EBI1 E8
NCLK_EBI1 F8
CS_EBI1 (NCS1) G8
CAS_EBI1 G7
RAS_EBI1 F7
W E_EBI1 F3
MN8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
ODT
CKE
CK
CK
CS
CAS
RAS
WE
DDR2 SDRAM
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VSS
VSS
VSS
VSS
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
A3
E3
J1
K9
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
1V8
C92 100n
C94 100n
C96 100n
C98 100n
C100 100n
C102 100n
C104 100n
C106 100n
C108 100n
C111 100n
VREF1
C116
100n
DQS0_EBI1 {4}
DQM0_EBI1 {4}
EBI1_DDR_A2 H8
EBI1_DDR_A3 H3
EBI1_DDR_A4 H7
EBI1_DDR_A5 J2
EBI1_DDR_A6 J8
EBI1_DDR_A7 J3
EBI1_DDR_A8 J7
EBI1_DDR_A9 K2
EBI1_DDR_A10 K8
EBI1_DDR_A11 K3
EBI1_DDR_A12 (SDA10) H2
EBI1_DDR_A13 K7
EBI1_DDR_A14 L2
EBI1_DDR_A15 L8
BA0_EBI1 G2
BA1_EBI1 G3
F9
CKE_EBI1 F2
CLK_EBI1 E8
NCLK_EBI1 F8
CS_EBI1 G8
CAS_EBI1 G7
RAS_EBI1 F7
W E_EBI1 F3
MN9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
ODT
CKE
CK
CK
CS
CAS
RAS
WE
DDR2 SDRAM
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VSS
VSS
VSS
VSS
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
A3
E3
J1
K9
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
1V8
VREF1
C117
100n
DQS1_EBI1 {4}
DQM1_EBI1 {4}
C93 100n
C95 100n
C97 100n
C99 100n
C101 100n
C103 100n
C105 100n
C107 100n
C109 100n
C112 100n
1V8
{3} EBI1_NRD/CFOE
{3} EBI1_NWE/NWR0/CFWE
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
R200 0R
R53 100k
R54 0R
R55 100k
1V8
E8
D8
C8
B8
A8
B7
A7
C7
A2
B2
C2
A1
B1
C1
D2
D1
D4
B6
A6
C6
B3
C3
B4
B5
C4
D6
E7
F8
C5
A5
MN10 DNP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
NC/A21
CLK
RESET
LATCH
WP
CE
OE
WE
VPP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WAIT
NC
VDD
VDD
VDDQ
VDDQ
VSS
VSS
VSSQ
VSSQ
F7
E6
E5
G5
E4
G3
E3
G1
G7
F6
F5
F4
D5
F3
F2
E2
D3
D7
A4
G4
E1
G6
A3
F1
G2
G8
1V8
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
C110 100n
C113 100n
C114 100n
C115 100n
D
C
G1
L3
L7
RFU1
RFU2
RFU3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
G1
L3
L7
RFU1
RFU2
RFU3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
{3} EBI1_NCS0
1
JP9
2
R56
470k
M58W R032KT_VFBGA56
VSSDL
E7
VSSDL
E7
{3,5} DDR_VREF
VREF1
MT47H64M8CF-3 -F
{4} EBI1_NAND_FSH_D[0..15]
MT47H64M8CF-3 -F
{3} PC5
{3,4} PC4
JP10
1
2
(NCS3)
SIP2
(RDY/BSY)
B
A
(NANDCLE)
(NANDALE)
{3} EBI1_NANDOE
{3} EBI1_NANDW E
{3} PC14
1V8
{3} PC8
1V8
IMPORTANT note about system booting:
The bootROM allows booting from the block 0 of a NandFlash connected
on CS3. However, the bootROM does not feature ECC (Error Checking and
Correction) on NandFlash.
Most of the NandFlash vendors do not guarantee anymore that block 0
is error free. Therefore we advise the bootstrap program to be located
into another device supported by the bootrom (DataFlash, Serial Flash,
SDCARD or EEPROM) and implement NandFlash access with ECC.
R57
R58
R59
R60
R61
R62
0R
0R
470k
0R
1k
470k
RE
WE
CE
RB
WP
R63
0R
DNP
D5
C4
D4
C7
C6
C8
C3
G5
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
MN11
CLE
AL E
RE
W E
CE
R/B
WP
LOCK
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
NAND FLASH
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
L9
L10
M1
M2
M9
M10
D3
G4
H8
J6
C5
F7
K3
K8
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
1V8
C118
C119
C120
C121
100n
100n
100n
100n
B
A
1/1
MT29F2G08ABDHC:D
A2 PP 08-apr-10
A Derek 05-Feb-10
REV MODIF. DES. DATE
AT91SAM9M10-G45-EK SCALE
EBI1_MEMORY
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
PP
VER.
REV.
A2
11-FEB-10
DATE
SHEET
6
12
8
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3
2
1
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